Reconfigurable Architecture Exploration for Speeding Up Execution of Code Generated from High-Level Specifications
نویسندگان
چکیده
Software generated from finite state machines targeted for standard embedded systems processors generally displays poor execution speeds. This paper evaluates an architecture that couples a standard processor with a reconfigurable unit in order to improve the execution speed of the generated code. A method for automatically partitioning the code is presented along with results obtained from simulation and profiling.
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